How to deliver on time in lower technology codes?

Over the years, we have seen a wide range of advances in semiconductor design services. The Semiconductor Industry Association (SIA) announced that the global semiconductor industry had sales of $ 468.8 billion in 2018 – the industry’s highest ever annual total and a 13.7 percent increase over 2017 sales.

As demand for semiconductor services continues to rise and the industry is witnessing a wider range of new technology innovations, we can clearly see a move towards lower geometries (7nm, 12nm, 16nm, etc.). The main drivers behind this trend are advantages in terms of power, range plus various other features that become possible with lower geometries.

The spread of lower geometries has given rise to business in a number of areas, especially in the sectors of mobility, communications, IoT, cloud, AI for hardware platforms (ASIC, FPGA, boards).

Delivering a lower technology design project on time is important in today’s dynamic and competitive market. However, there are many unknowns at lower geometry that affect project / product planned delivery. By remembering the elements below, it is possible to ensure timely delivery at lower geometry nodes.

1. Low cost modeling for technology node

A chip design manager provides the required strong technical leadership and has overall responsibility for the integrated circuit design.

For lower geometry designs, engineers must define the spec-to-silicon activities, sequencing them in the right order, estimating the resources needed, and estimating the time required to perform the tasks. At the same time, they need to focus on reducing overall system costs while meeting specific service requirements. The following are the actions that engineers can take to optimize costs:

Use multiple patterns

Use appropriate design-for-test (DFT) techniques

Utilize mask making, interconnections and process control

On different layout methods, because node downscaling is no longer cost-effective. For continuous performance improvement along with cost control, some companies are now pursuing monolithic 3D ICs rather than a conventional plan implementation as this can provide 30% power savings, 40% performance boost and reduce costs by 5-10% without changing over to a new node.

2. Advanced data analysis for smart chip manufacturing

In the chip-making process, a large amount of data is generated on the fab floor. Over the years, the amount of this data has continued to grow exponentially with each new technology node dimension. Engineers have played instrumental roles in generating and analyzing data with the goal of improving predictable maintenance and yield, improving R&D, improving product efficiency and more.

Applying advanced analysis in chip manufacturing can help improve the quality or performance of individual components, cut down on quality assurance test time, increase throughput, increase equipment availability, and reduce operating costs.

3. Effective management of supply chains

As new technology is often released faster than the R&D timeline, everyone in the chip manufacturing industry faces a problem in IC supply chain management. The big question is: how to improve efficiency and profitability in this scenario.

The answer is faster decision-making and efficient integration of various suppliers, customer requirements, distribution centers, warehouses and stores, so that merchandise is produced with end-to-end supply chain visibility and distributed in the right quantities, at the right time at the right place to minimize overall system costs. .

4. Timely delivery process

Improved delivery to the customer is a core part of semiconductor design services. It includes setting up order registration to work with runtime orders, cloud computing optimization, logistics and transferring the end product to a customer – while keeping up to date with all the necessary information at every step. Planning the complete flow ensures that no critical deadlines for the project are missed.

To overcome delays, semiconductor design companies can:

  • Minimize the use of custom streams and switch to location & route streams for better physical data tracking capabilities.

  • Set and comply with fast response time to client requirements and change requests.

  • Get real-time information from spec to silicone availability regarding semiconductor design flow, location, reservation and quantity.

  • Ensure collaboration between teams working on the project.

  • Focus on criticality analysis – reduces the risk of malfunctioning in the design to prevent business stoppers.

  • Make use of expertise in multiple project management tools.

  • Adopt better technologies (TSMC, GF, UMC, Samsung), better methodology (Low power consumption and high speed performance), better tools (Innovus, Synopsys, ICC2, Primetime, ICV).

How are eInfochips positioned to serve the market?

Whether you want to design innovative products faster, optimize R&D costs, improve time to market, improve operational efficiency or maximize return on investment (ROI), eInfochips (an arrow company) is the right design partner.

eInfochips has partnered with many worldwide companies to contribute over 500 product designs with more than 40 million implementations worldwide. eInfochips has a large pool of engineers specializing in PES services, focusing on in-depth R&D and new product development.

In order to be able to deliver the product to the market in a short time, eInfochips provides ASIC, FPGA and SoC design services based on standard interface protocols. It includes:

  1. Unsubscribe services in frontend (RTL design, verification) and backend (Physical design and DFT)

  2. Turnkey design services that cover RTL to GDSII and design layout

  3. Use of reusable IPs and frameworks that help the company in short product development time and cost for faster and right time to market

This blog was originally published on eInfochips.com.